1. Field of the Invention
The present invention generally relates to digital-to-analog converters, and more particularly to a digital-to-analog converter having resistor networks and switches. More specifically, the present invention is concerned with a digital-to-analog converter having the following input-output conversion characteristic, EQU Vout=Vin.multidot.X/2.sup.n
where Vin denotes an input voltage, X denotes a digital input signal, n denotes the number of bits of the digital input signal X, and Vout is an analog output voltage.
2. Description of the Related Art
Digital-to-analog converters (hereinafter simply referred to as D/A converters) are widely used in various electronic circuits, such as output circuits of digital systems. In general, it is required that D/A converters operate at high speeds and precisely convert digital input signals into analog output signals.
FIG. 1 illustrates a D/A converter having two resistor networks. As shown, the D/A converter comprises a high-order-bit-side circuit 10 and a low-order-bit-side circuit 12, which respectively operate in response to high-order bits of a digital input signal and low-order bits thereof. The circuit 10 comprises a first resistor network NT1 composed of resistors R11-R1K connected in series, and switches S11-S1K and S21-S2K respectively connected to first and second ends of the resistors R11-R1K. The circuit 12 comprises a second resistor NT2 network composed of resistors R21-R2L connected in series, and switches S31-S3L respectively connected to ends of the resistors R21-R2L and an output terminal TO. The resistors R11-R1K have identical resistance values, and the resistors R21-R2L have identical resistance values. The circuit 10 is coupled to the circuit 12 via unit-gain buffer amplifiers A1 and A2. V.sub.RP denotes a positive reference voltage input, V.sub.RN denotes a negative reference voltage input, V.sub.1i and V.sub.1o denote input and output voltages of the buffer amplifier A1, V.sub.2i and V.sub.2o denote input and output voltages of the buffer amplifier A2, and Vout denotes an analog output voltage of the D/A converter.
The high-order-bit-side circuit 10 generates a high-order-bit-side output signal from an analog input voltage Vin (=V.sub.RP -V.sub.RN). More specifically, one switch S1Y among the switches S11-S1K and one switch S2Y among the switches S21-S2K are turned ON in response to high-order bits of a digital input signal. More specifically, the switches S11-S1K and S21-S2K are controlled by switch control signals obtained by decoding high-order bits Dt-Ds+1 of the analog input signal by means of a decoder 30.
In FIG. 1, the switches S1K-1 and S2K-1 are ON, and the other switches are OFF. Output voltages V.sub.1i and V.sub.2i of the circuit 10 are written as follows: EQU V.sub.1i =(V.sub.RP -V.sub.RN).multidot.Y/K+V.sub.RN EQU V.sub.2i =(V.sub.RP -V.sub.RN).multidot.(Y-1)/K+V.sub.RN
where Y.ltoreq.K, and Y is a natural number. The output voltages V.sub.1i and V.sub.2i of the circuit 10 are applied to the buffer amplifiers A1 and A2, which respectively output the output voltages V.sub.1o and V.sub.2o to the low-order-bit-side circuit 12.
One of the switches S31-S3L is selected in response to low-order bits of the digital input signal. More specifically, the switches S31-S3L are controlled by switch control signals obtained by decoding low-order bits Ds-DO of the digital input signal by means of a decoder 40. In FIG. 1, switch S33 is ON, and the other switches are OFF. The analog output voltage Vout obtained at the output terminal TO is written as follows: EQU Vout=(V.sub.1o -V.sub.2o).multidot.(Z-1)/L+V.sub.2o
where X.ltoreq.L, and Z is a natural number and indicates a selected resistor.
The buffer amplifiers A1 and A2 are unit amplifiers, and thus EQU V.sub.1o =V.sub.1i, v.sub.2o =V.sub.2i.
By substituting this relationships into the above equation, the analog output voltage Vout is expressed as follows: ##EQU1## When X is written as (Y-1).multidot.L+Z-1, K.multidot.L=2.sup.n, and thus X is the digital input signal having a value defined by the following: EQU 0.ltoreq.X.ltoreq.2.sup.n.
As a result, the D/A converter shown in FIG. 1 functions as an n-bit D/A converter which converts the digital input signal X into the analog output voltage Vout in the following manner: EQU Vout=(V.sub.RP -V.sub.RN).multidot.X/2.sup.n +V.sub.RN.
However, the D/A converter shown in FIG. 1 has the following disadvantages. It is necessary to use the buffer amplifiers A1 and A2 in order to connect the circuits 10 and 12 to each other because the output impedance of the circuit 10 does not match the input impedance of the circuit 12.
As shown in FIG. 2A, the unit-gain buffer amplifier can be formed with an operational amplifier. The operational amplifier shown in FIG. 2A comprises seven field effect transistors. The operational circuit shown in FIG. 2A has a symbol shown in FIG. 2B.
The buffer amplifiers necessarily have offset voltages. In other words, buffer amplifiers having no offset voltages are not available. Hence, the output voltages V.sub.1o and V.sub.2o of the buffer amplifiers A1 and A2 have offset voltages .sub..DELTA.1 and .sub..DELTA.2 as follows: EQU V.sub.1o =V.sub.1i +.sub..DELTA.1, EQU V.sub.2o =V.sub.2i +.sub..DELTA.2.
In this case, the analog output voltage Vout is written as follows: ##EQU2## When V.sub.RN =0 for the sake of simplicity, the analog output voltage Vout is expressed as follows: EQU Vout=V.sub.RP .multidot.X/2.sup.n +(.sub..DELTA.1 -.sub..DELTA.2).multidot.(Z-1)/L+.sub..DELTA.2.
For example, when Y=1 and Z=L, that is, X=(1-1).multidot.L+L-1=L-1, the output voltage Vout(I) is expressed as follows: ##EQU3## When Y=2 and Z=1, that is, X=(2-1).multidot.L+1-1=L, the output voltage Vout(II) is expressed as follows: ##EQU4## The difference Vdiff between the above-mentioned output voltages Vout(I) and Vout(II) is written as follows: ##EQU5##
It will now be assumed that a power supply voltage is equal to 5 V, the digital input signal X is an eight-bit signal, and the offset voltages of the buffer amplifiers A1 and A2 are equal to 15 mV and -15 mV, respectively. That is, V=V.sub.RP =5[V], K=L=16, .sub..DELTA.1 =15[mV], and .sub..DELTA.2 =-15[mV]. By inserting these values into the equation regarding the voltage difference Vdiff, the following is obtained: ##EQU6##
However, in the above case, the voltage difference Vdiff must be LLSB (Least Significant Bit) and be positive. This shows that the analog output voltage does not have linearity and that the buffer amplifiers 1A and 1B degrade the D/A conversion characteristics. Further, due to the frequency characteristics of the buffer amplifiers 1A and 1B, the D/A converter has a limited operation frequency, and hence a limited operation speed.